 |
| Skema Rangkaian Jam Digital |
Kumpulan Skema Elektronika- Jam Digital dengan Seven Segmen. The Clock Controller V1.1was designed to be an exemplary of using 'C' language to control timer0interrupt, 7-segment LED and keypad scanning. It provides 1-bit sink currentdriving output, for driving a relay, opto-triac, say. Many projects requiring7-segment display and keypad interfacing may get the idea from the Clockcircuit and software.
Hardware
Figure 1 shows a circuitdiagram of the Clock Controller V1.1. P10-P1.7 drives 7-segment commonanode LED with sink current. P3.0-P3.3 also drives a base pin of 4-PNPtransistor, 2n2907 with sink current. As shown in the figure, the 2nd 2-digitLED that connected to P3.2 and P3.3 is rotated 180 degrees to the 1st 2-digitallowing the pt. segment to be used for 1 second blinking. P3.0-P3.3 alsoconnects four momentary switches while the other legs are tied to inputport P3.4. During display and key switch scanning, a logic '0' is shiftedfrom P3.0 to P3.3, if there was a key pressed, P3.4 then became low.P3.7 is a 1-bit sink current driving, an example in the circuit uses a2n2907 to drive a small electromechanical relay 5V, say.
Source: http://www.kmitl.ac.th
0 comments:
Post a Comment